グローバルCOE国際シンポジウム

Date

Time

February, 18th , 2013

9:30-17:45

Place
Royal Blue Hall (Lectures) and Kuramae Hall (Posters) Tokyo Tech Front, 2-12-1 Ookayama,
Meguro-ku,Tokyo
Fee
Free
Registration
Please see registration page.

 

PREFACE

Continuous advances in the performance and chip complexity of integrated circuits according to the Moore’s law based on the miniaturization of transistors over the past 50 years have enabled the Information Age for 21st century society. Today, however, the minimum feature size of transistors is in nanometer range and further scaling can be achieved not simply by miniaturization, but with introduction of new materials or new device concepts.
The purpose of this international symposium is to bring together world’s leading scientists in the field of nanoelectronics and discuss about future directions of nanodevice and photonics technology.

Invited Speakers: W.I. Milne (Cambridge Univ.), S. Deleonibus (CEA-LETI), K. Banerjee (UC Santa Barbara), H. Wong (Hong Kong City Univ.), A. Toriumi (Tokyo Univ.), K. Shiraishi (Tsukuba Univ.), T. Mogami (PETRA), K. Tsutsui (Tokyo Tech).

Sponsorship: The Excellent Graduate School on “Photonic-Integrated Core-Electronics” assigned by MEXT, Japan, the Quantum Nanoelectronics Research Center and Frontier Research Center, Tokyo Institute of Technology, the IEEE EDS Japan Chapter and the ECS Japan Chapter.
Technical supports: The Silicon Technology Division of JSAP.

Co-organizers: Shunri Oda and Hiroshi Iwai.
Shunri Oda
(Tokyo Institute of Technology)
Hiroshi Iwai
(Tokyo Institute of Technology